The present invention concerns a Direct Memory Access (DMA) controller installed in a computer system, and especially reading write-only registers in such a DMA controller.
Although ISA (Industry Standard Architecture) and EISA (Extended ISA) buses are conventional in system buses used in personal computers, recently a Peripheral Component Interconnect (PCI) bus has been employed in desktop type personal computers to increase the speed of data transfer and organize system architecture, independently of the kind of processors.
In a PCI bus, block transfer is the basis of substantially all data transfer. Transfer of each block is done by burst transmission. For example, a maximum data transfer speed of 133 megabytes/sec is used when a data bus has a width of 32 bits. Therefore, when a PCI bus is used, data transfer between I/O devices and between a system memory and an I/O device is executed at a high speed and system performance is increased.
Recently, PCI buses have been used not only in desktop type personal computers, but in portable personal computers such as notebook computers. Since the specification of the PCI bus does not support DMA transfer supported in the ISA bus, it is necessary to install a Direct Memory Access Controller (DMAC) in the PCI bus system to use an ISA device with the PCI bus system. The DMAC supports two or more channels, and has several I/O registers for maintaining the DMA transfer mode and an address by each DMA channel.
However, the majority of these I/O registers are write-only registers, making them inconvenient to debug. Since both readable/writable I/O registers and write-only I/O registers in the DMAC are usually composed of a flip-flop, hardware logic for reading/writing data from the registers is comparatively easily changed so that data from a write-only register can be read under an I/O address corresponding to the write-only I/O register. However, if the I/O address is used so that this write-only register can be read, a problem arises with the compatibility of the ISA standard architecture.
The purpose of the present invention is to read a write-only register, compatible with ISA standard architecture.
Another purpose of the present invention is to provide a DMA controller capable of reading write-only registers therein.